1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device including a protection ring and a method of fabricating the protection ring.
2. Description of the Prior Art
With the trend of miniaturization, diversification and always higher performances of the portable electronic products and peripherals, three-dimensional (3D) interconnects technique has become one of the important developing aspects of the current package technology in order to achieve thin structure and high integration of the semiconductor devices. The 3D interconnects technique can be used to improve the abilities and the capacities of a semiconductor packaged element.
The through silicon via (TSV) technique, which aims at solving the problems of interconnection between the wafers, is a 3D interconnects technique. With the TSV technique holes are drilled in the wafer by etching or by laser means, the holes are then filled with conductive materials, such as copper, polysilicon or tungsten, to form vias, i.e. conductive channels connecting inner regions and outer regions. Finally, the wafers or the dice are thinned to be stacked and bonded, which then become three-dimensional stack integrated circuits (3D stack IC). The package size of the 3D stack IC is of the size of the dice, in order to meet the requirements of miniaturization.
TSV technique, as opposed to the conventional stack package of wire bonding type, stacks the wafers or the dices vertically to reduce the length of the conductive lines, which means that the inner connection distances can be shortened. Therefore 3D stack ICs perform better in many ways, like faster transmission and lower noise, especially for applications in CPU, flash memories and memory cards. Additionally, TSV technique can also be employed for heterogeneous integration of different ICs, like stacking a memory on a CPU for example.
The TSV technique processes for semiconductors can be divided into two types, namely via first or via last, in accordance with the order of the formation of the vias. For the via first process, the vias produced with the TSV technique are formed before the back end of the line (BEOL) process. Conversely, for the via last process, the vias produced with TSV technique are formed after BEOL process.
In addition, protection rings may provide insulating effect when disposed between the vias in the package region and the transistors in the active area region. During the formation of the protection rings, during the step of filling the protection ring with insulating material, the accumulated thickness of the insulating material layer may increase the stress imposed on the semiconductor substrate, and may accordingly induce damages in the semiconductor substrate. Consequently, how to improve the protection ring process in order to prevent abnormal performances of semiconductor devices caused by damages of semiconductor substrate is an important issue in this field.